Usually, a terminal for connection to a semiconductor chip (hereinafter referred to as a connecting terminal) is formed on a principal surface (front face) of a wiring board. Nowadays, the density of the connecting terminals has been becoming high, and therefore the distance (pitch) of the arranged connecting terminals has been narrow. In view of this, a wiring board employing a Non-Solder Mask Defined (NSMD) where a plurality of connecting terminals is disposed in the same opening of a solder resist has been proposed.
However, in the case where the plurality of connecting terminals are disposed in the same opening, a solder coated on the surface of the connecting terminal possibly flows out to an adjacent connecting terminals, resulting in a short circuit between the connecting terminals. Accordingly, to prevent the solder coated on the surface of the connecting terminal from flowing out to the adjacent connecting terminals, there is provided a wiring board with an insulating partition wall disposed between each of the connecting terminals (for example, see Patent Document 1).
However, with the partition wall, this partition wall prevents a flow of underfill to be filled up in a clearance between an electronic component and the wiring board when mounting the electronic component (for example, a semiconductor chip). In view of this, the underfill is not uniformly filled up in the clearance between the electronic component and the wiring board. This may cause a deficiency such as a breakage and corrosion.    Patent Document 1: JP-A-2009-212228